features ? up to 125 msps sample rate ? on-board differential clock driver ? controlled impedance pcb for critical signals ? high-frequency, low-distortion sma connectors for i/o applications ? evaluation and characterization of the spt9101 ? guide for designing with the spt9101 ? engineering system prototype aid AN9101 evaluation board application note general description the eb9101 evaluation board is intended as a tool for device evaluation and characterization and to demonstrate the performance of the spt9101 (track-and-hold amplifier). the spt9101 is a high-speed track-and-hold amplifier ca- pable of sampling up to 125 msps with 8-bit resolution, and up to 50 msps with 12-bit resolution. it is a second source for the analog devices ad9101. the devices are pin compat- ible, except the spt9101 does not require an external bootstrap capacitor. block diagram this application note is a supplement to the data sheet and includes more detailed information on the interfacing circuits required to operate the spt9101. the evaluation board is designed to accommodate a wide variety of applications. it can be easily modified to suit a specific application by using the prototype area provided. contact the fairchild applica- tions engineering department if assistance is needed. this application note describes in more detail the following functional blocks of the evaluation board: power supplies and grounding, analog input/output, sample clock circuitry and layout. spt9101 (lcc or soic) clk nclk hcmp96850 le - + +5 v -5 v analog input clock input analog output +5 v gnd -5 v free datasheet http:///
2 10/22/97 AN9101 power supplies and grounding the eb9101 requires +5 v and -5.2 v supplies for all components on the evaluation board, including the compara- tor and the spt9101. the supplies are adequately de- coupled, but clean power supply sources are highly recom- mended. note that all power is returned to a single common analog ground. this is the recommended arrangement when designing with this part. for example, if the spt9101 is located on the front-end of an adc, or if used as a deglicher for a high-speed dac, it will be located in the analog section. before connecting any power supply to the evaluation board, set each supply to its correct value and then turn off the supplies. ensure all supplies are connected and preset before power is applied. fairchild recommends that both supplies be powered-up simultaneously. after power-up, verify the supply voltages are within specifications before proceeding. if adjustments are necessary, reference your measurement to the analog ground. analog input/output the analog input signal can be fed directly through the sma connector into v in1 . there are two line termination resistors, r8 associated with the lcc package and r14 associated with the soic package. this design was used to ensure proper line termination with the shortest stub. that is, the resistor is as physically close to the spt9101 as possible. note that the termination is a chip style resistor that exhibits a low parasitic inductance and capacitance. the spt9101 has a fixed overall gain of four. the recom- mended maximum output is 2.7 v or v in max = 0.675 v. figure 1 shows the transfer function of the spt9101. the overdrive saturation characteristic can by observed in the transfer function, with a nonlinear recovery. fairchild does not recommend operating in this region. if your design will exceed the recommended input level, fairchild highly recom- mended using high-speed schottky diodes for clamping the signal. figure 2 shows an example circuit using schottky diodes for the input limiting. the eb9101 is tested and verified to a 0.5 v input range. in addition, dynamic performance at 125 msps is verified on the evaluation board. the output of the spt9101 is connected to its associated sma output connector through a 27 w series resistor. since this resistor is there to accommodate any improperly matched stub connection, its value can be changed to fit the users purpose. the eb9101 uses either the lcc or soic package versions of the spt9101. use vout_1 if the soic package is installed and vout_2 if the lcc is installed. it is not recommended to operate both devices on this board simultaneously. degradation of performance of the spt9101 can be expected if operated in this manner. sample clock circuitry the evaluation board uses an hcmp96850 high-speed com- parator in a 16-pin dip package. the comparators propaga- tion delay is typically 2.4 ns with a very low offset of 3 mv and a minimum tracking bandwidth of 300 mhz. the comparator has been set up in a feedthrough mode by grounding the latch enable pin (ecl high), thus disabling the latch mode. the comparators input common mode range is 2.5 v. fairchild recommends that the clock input be generated from a signal generator with a sinewave amplitude of 1.0 v p-p symmetrical around ground, and that r2 be open, r3 be shorted and r4 be equal to 50 w for proper line termination. with this input mode, a modest duty cycle adjustment is possible by adjusting potentiometer r1 to various dc levels on the comparators non-inverting input. if a sinewave signal is not available then an ecl or ttl level signal may be used, with the proper voltage divider on the input to the comparator. with an ecl input it is recommended that the resistor arrangement on the input of the comparator be the same as for a sinewave input. in addition, adjust r1 to approximately -1.3 v to be a mid-level for a nominal ecl signal for the comparator to operate against. with a ttl input several aspects will need to be considered: the drive capability of the clock input; and the optimum termination for the clock signal. using two appropriately selected resistors the amplitude of the signal will need to be divided to below the common mode range (less than 2.5 v). fairchild recommends the addition of resistor r2 for proper termination of the clock signal, if these two resistors do not provide proper termination. for proper comparator opera- tion, adjust potentiometer r1 to the mid-scale of the com- parator input signal. the output of the comparator is differential ecl. the clk_in of the comparator and clk of the spt9101 are in phase (note the double inversion). the outputs of the comparator use parallel termination of 270 w over 150 w (referenced to ground and -5.2 v). this parallel termination is located as close to the receiver end as physically possible to minimize reflection of the clock signals. in addition, there are clock test points (with an associated ground pad for shorter reference ground length) for a truer representation of the probed clock signal for timing purposes. free datasheet http:///
3 10/22/97 AN9101 layout this evaluation board is laid out with four layers: two signal layers with controlled 50 w impedance; an analog ground layer; and a power distribution layer. decoupling surface mount capacitors are mounted as close as possible to the ics and filter capacitors at the power input pins. ferrite beads (fb1 and fb2) are used to further filter the spt9101 power supply from the other associated circuitry onboard that uses the same power supplies. the evaluation board has many capabilities and features. easy connect, clip-on test points for power supplies (+5 v and -5 v), sma connectors for sample clock input, analog input and track and hold output and a comparator with ecl output to drive the sample clock. the assembly is a self-contained building block that may be used for many system applica- tions. there is a dip footprint for a user configurable prototyp- ing area on the left side of the board for sample clock circuitry. figure 1 - transfer function setup and calibration the following setup should be performed to verify functional operation of the evaluation board. 1. set and connect the power supplies as outlined in the power supplies and grounding section. 2. setup a 20 mhz sinewave, 1 v p-p signal and connect it to the clk_in sma. adjust r1 for a 50% duty cycle while monitoring the clk1 test pad. 3. setup a 1 mhz sinewave 1.0 v p-p signal and connect it to the vin1 sma. in addition, ensure that the two signal generators are synchronized together. 4. using an adequate bandwidth scope, observe a signal that is similar to a sinewave with 20 steps. note: there will be some normal over or undershoot at the time of going in and out of hold mode. figure 2 - input limiter circuit spt9101 (lcc or soic) r_limit schottky diodes (back-to- back, both polarities. volt limit 0.7 v) -0.8 v in (volts) spt9101 transfer curve -1.2 -0.4 0.0 +0.4 +0.8 +1.2 -4.0 v out (volts) -3.0 -2.0 -1.0 0.0 +1.0 +2.0 +3.0 free datasheet http:///
4 10/22/97 AN9101 table i - parts list # reference description part number qty vendor 1 c1, 2 ecs-t1ay475r capacitor 4.7 m f, 10 v 2 panasonic/any 2 c3, 4 ecs-t1ay225r capacitor 2.2 m f, 10 v 2 panasonic/any 3 c5-c16 ecu-v1h103kbm chip cap smd 1206 .01 m f 12 panasonic/any 4 clk_in, v in 1 901-144-8 pc mount sma connector 3 amphenol rf/ any 5 fb1-2 exc-elsa-35 ferrite bead 2 panasonic/any 6 gnd1-2, agnd, +5 v, -5.2 v, 40f6045 test point .075" 7 newark/any +5 proto -5 proto 7 r1 3266w-202-nd potentiometer, 2 w , 12t 1 bourns/any 8 r2 omitted 9 r3 0.0ebk-nd socketed resistor, 1/8 w 1 digi-key 10 r4 51ebk-nd socketed resistor, 1/8 w 5% 1 digi-key 11 r5,r13 erj-8enf270 resistor, 27 w smd 1206 2 panasonic/any 12 r6-7 erj-8enf102 resistor, 1 k w smd 1206 2 panasonic/any 13 r8, r14 erj-8enf49r9 resistor, 49.9 w smd 1206 2 panasonic/any 14 r9-10 erj-8enf151 resistor, 150 w smd 1206 2 panasonic/any 15 r11-12 erj-8enf271 resistor, 270 w smd 1206 2 panasonic/any 16 u1 hcmp96850sid h/s comparator 1 fairchild 17 u2 spt9101scp sample and hold 0 fairchild 18 u3 spt9101scp sample and hold 0 fairchild 19 n/a eb9101 rev c printed circuit board 1 sas 20 n/a ed5045-nd sockets for resistors 6 digi-key/any 21 n/a 1902-nd 4-40 nylon hex standoffs 4 digi-key/any 22 n/a h143-nd pan head 4-40 screws 4 digi-key/any free datasheet http:///
5 10/22/97 AN9101 figure 3 - detail schematic free datasheet http:///
6 10/22/97 AN9101 figure 4 - component side silk free datasheet http:///
7 10/22/97 AN9101 figure 5 - solder side silk free datasheet http:///
8 10/22/97 AN9101 life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. www.fairchildsemi.com ? copyright 2002 fairchild semiconductor corporation free datasheet http:///
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